A content addressable memory CAM architecture is an array of individual CAM cells. Each CAM cell consists of a data storage unit and comparison circuitry. The storage unit is used for storing data and the comparison circuitry is used to compare the compare-data with the data stored in storage unit and providing a signal indicating a match or mismatch. This signal is fed to a priority encoder for selecting one of the match signals, in the event of multiple signals, as the final output.
Throughout this disclosure, logical “1” refers to and is interchangeable with a logical “High” corresponding to a voltage VDD, while logical “0” refers to and is interchangeable with a logical “Low” corresponding to GND. FIG. 1 illustrates a PRIOR ART 9-transistor CAM cell 100 using a NOR configuration. The CAM cell 100 includes an SRAM cell for data storage, comprising a pair of cross-coupled inverters formed by transistors 111, 112, 113 and 114 and a pair of access transistors 115 and 116. The comparison circuitry of the CAM cell 100 consists of a pair of pass transistors 117 and 118. The conducting terminals of the pass transistor 113 and 111 are connected in series between the supply voltage VDD and ground GND while the control terminals are connected to the common conducting terminals F of pass transistors 114 and 112. The conducting terminals of pass transistor 114 and 112 are also connected in series between VDD and GND while the control terminals are connected to the common conducting terminals T of pass transistors 113 and 111. The conducting terminals of pass transistors 115 and 116 connect nodes T and F to the corresponding bit lines BLT and BLF while the control terminals are connected to word line WL. The pass transistors 117 and 118 are connected in series between bit lines BLT and BLF and the common node is labeled as the Bit-Match node. The control terminals of transistors 117 and 118 are coupled to nodes F and T, respectively. Output transistor 119 is coupled between the match line ML and ground GND and its control terminal is connected to the Bit-Match node of the CAM cell.
The READ and WRITE operations of this CAM cell 100 are the same as those of a standard 6-transistor SRAM cell, wherein the precharge state of bit lines BLT and BLF is logical “High”. During the SEARCH operation, bit lines BLT and BLF are initially precharged to logical “Low” and ML is precharged to logical “High”. Then the comparand bit is placed on BLT and its complement is placed on BLF. If the comparand bit matches with the data bit stored in the CAM cell, then one of the pass transistors 117 or 118 drives the Bit-Match node to logical “0” and therefore ML remains at logical “High”, indicating a match. On the other hand, if there is a mismatch between the applied comparand bit and the data bit stored in the CAM cell, then one of the pass transistors 117 or 118 drives the Bit-Match node to “VDD-Vtn”, thereby turning the pull-down transistor 119 on and pulling down ML indicating a mismatch.
The CAM cell 100 requires a precharge to logical “Low” operation for bit lines and a precharge to logical “High” operation for ML when a SEARCH operation is requested if the default standby state is for a READ or a WRITE operation. Conversely, if the CAM cell 100 is ready for a SEARCH operation in its default standby state, then the bit lines must be precharged to logical “High” and ML is thereby discharged when a READ or WRITE operation is requested. It is known that both bit lines and ML impose a heavy capacitive load on their drivers and prechargers. Therefore, CAM cell 100 consumes more power and provides larger READ/WRITE/SEARCH access times.
FIG. 2 illustrates another PRIOR ART 9-transistor CAM cell 200 using a NOR configuration. The only difference between CAM cell 100 and 200 is that CAM cell 200 is provided with dedicated lines CBLT and CBLF for the search operation as shown in the FIG. 2. Thus, CAM cell 200 provides more flexibility in the timing of READ, WRITE and SEARCH operations but at the cost of hardware overhead required for controlling the dedicated compare bit lines CBLT and CBLF.